SystemVerilog has several useful additions for FPGA engineers, but tool support has been slow to materialise. For the moment, I’ve kept to the few features that

SystemVerilog has several useful additions for FPGA engineers, but tool support has been slow to materialise. For the moment, I’ve kept to the few features that Xilinx Vivado and Yosys http://www.clifford.at/yosys/ http://www.clifford.at/yosys/ are both happy with, such as enums, logic data type, and always_ff etc. I’ve not used VHDL in anger, so can’t give you a useful opinion there.