SIMT became an abstraction that was lowered to SIMD at compile time to instead being the abstraction used when targeting the underlying hardware. > Furthermore

SIMT became an abstraction that was lowered to SIMD at compile time to instead being the abstraction used when targeting the underlying hardware. > Furthermore, the PTX is substantially similar PTX is just a (forwards-compatible) intermediate representation. > The per-thread instruction pointers is pretty transparent in most code Except control flow divergence, which is what changes there, yes. > Although, I guess both of those GPUs can laugh at AVX512, where the execution masks are explicitly handled by the assembly programmer. But I don't know if explicit execution masks is necessarily a bad thing (its the job of the compiler instead of the decoder or whatever...) That's a very good question. AVX-512 with its masking abilities was substantial progress over AVX2. For a CPU, having secondary instruction flows just for the vector units just isn't a (reasonable) option though. If there wasn't the 10nm issues, the next Xeon Phi would have been very interesting on that front. You might also want to look at the Fujitsu A64fx on the Arm side, used in Fugaku. (building a supercomputer with just CPUs, no GPUs) We'll see what will be there in the future... will certainly be very interesting.