> BayBal, since you're an expert in Semi, I wonder if you can fill in the blanks? An expert? Ahahh, I never even had formal education in the field, just been t

> BayBal, since you're an expert in Semi, I wonder if you can fill in the blanks? An expert? Ahahh, I never even had formal education in the field, just been trying to enter it, and start studies in it for a few years. My only real experience with ICs was with a company developing a fancy synchronous rectifier chip what was capable of doing few more tricks with the output waveform besides rectification, and that was mostly just hanging around, and doing complete trivialities like routing, or minimal layout wiggling. I was more useful there as a coffee porter. > How much do you estimate the full chip manufacturing cost for this would be ? I don't know how many wafers they buy. I don't know whether they ordered masks from TSMC, or somebody else. I don't know how short they want lead times to be. I don't know if they want to have any device inspection provided. I don't know if they have any agreements on repeated runs, or a flexible capacity purchase. I don't know if they order test, and packaging from TSMC. From a man who was on Allwinner's original A10 chip team, I heard that the most bare bones 65nm run without mask cost, inspection, or packaging was possible at 1k wafers at $2400-$2500 in 2013-2014 by paying cash 1y in advance. Today, I'm not even sure if clients are even allowed to, or can order masks on the side these days for latest processes. The universal advice I heard is that you don't get into 300mm game without at least $10m, or better $20m if you have a brand new, untested design.