> using a commercial FPGA to ASIC service This was not an FPGA conversion. "Commercial FPGA to ASIC service" usually refers to Altera/Intel's HardCopy or Xili

> using a commercial FPGA to ASIC service This was not an FPGA conversion. "Commercial FPGA to ASIC service" usually refers to Altera/Intel's HardCopy or Xilinx's EasyPath. EasyPath is where Xilinx sells you defective FPGAs for way cheaper, but with just enough of the right parts of the fabric working that your design can still fit and work properly. HardCopy is where Altera sells you a small number of metal mask layers to implement your design on a much smaller/faster sea-of-gates style ASIC that mimics the non-reprogrammable parts of the target FPGA. The Raspberry Pi Foundation did neither of these things. They tested their design on an FPGA, which is common, and then used standard cell libraries and IP blocks provided by the fab and their partners to get through the normal ASIC workflow. It turns out it's just easier and faster to tell the tools to automatically place and route the core complex than to do a careful floorplan. Also given that the RP2040 is apparently "very overclockable" (the PIO bitbanged HDMI output bumped the clock to something like double the nominally guaranteed maximum), the merits of doing it this way seem sound.