Seems to be mainly focusing on the front end (schematic) part of the design, which is smart because PCB layout is a much bigger can of worms. Some casual overly

Seems to be mainly focusing on the front end (schematic) part of the design, which is smart because PCB layout is a much bigger can of worms. Some casual overly-critical observations (from the PoV of an embedded hobbyist): This really consists of: (1) a "smart netlist" not dissimilar to Verilog, as an alternative of traditional graphics-based schematic capture (2) on top of it, automatic component selection (3) pre-defined bus types and topologies to simplify interconnection. The value of #1 is debateable. For digital-heavy circuits, I do prefer text-based representation, but of course it depends on how terse it is. However when it comes to analog, the graphical representation is way more powerful, as it naturally reveals the topology of the circuit, while anything text-based obscures it by design. The schematic generated by the tool is nowhere close to human-readable, let alone modifyable (you aren't supposed to modify that anyway if the netlist is the source of truth), and AFAIK there has never been a drive to automate netlist-to-schematic, even with metadata annotation. #2 sure is a bold proposal, and TBH I see it as the "core competency" of a schematic engineer --- something you cannot effectively automate out of. Even if you could, not sure real engineers would actually follow the, uh, "advice" from such tools. For smaller and commonly used things (passives, discrete semiconductors, building-block ICs) of course there is value, but arguably this is a feature, not a product. Then for bigger things that often dictate the rest of the design, just having a part handed to me is clearly not enough --- a good engineer needs to understand the multitude of trade-offs and provide justification on why a specific part / part group is chosen, more often than not based on part quantitative (maybe automate-able) and part qualitative (unlikely to be automated) measures. #3 is where the money resides and synergizes with #1, although arguably tools like this (so-called pinout editor or configuration tool) had always been a first-party thing. Very useful for high pin count digital work. The database part of this needs to be hand-curated, but it only needs to scale as fast as the manufacturer can churn out new parts. Also nit: It's almost always better to use an established general-purpose PL as the base, if programmability is the selling point. See Chisel, Bluespec, PCBDL, SKIDL, PyPCB, ... If you insist you can still build a symbolic representation like Tensorflow, but having to learn yet another esoteric PL is a really big barrier even for coding people.