There are also some POWER processors that move most of the memory controller off-chip, and use a media-agnostic high speed serial link between the CPU and each

There are also some POWER processors that move most of the memory controller off-chip, and use a media-agnostic high speed serial link between the CPU and each memory controller chip. That allows for a lot of flexibility in tuning for memory capacity or bandwidth, at the expense of a bit of extra latency. Those CPUs end up having all of their IO in the form of high speed serial links, some used for PCIe, some for NVLink, some for CAPI/OMI.