A few observations about what's changed since this was written: The layout shown in Figure 2.1 with a traditional shared Front Side Bus linking CPUs to the nor

A few observations about what's changed since this was written: The layout shown in Figure 2.1 with a traditional shared Front Side Bus linking CPUs to the northbridge is a long-dead design, having been retired from mainstream products by AMD around 2003 and by Intel around 2008. Since then, the northbridge and memory controllers have been on the CPU die(s) for almost all products. AMD's Zen 2 and later desktop/server CPUs split the northbridge back out to a separate die ("IO die"). All recent x86 processors that I can think of off the top of my head have the PCIe ports provided by the northbridge (which means it's usually part of the CPU die itself). The southbridge is connected to the northbridge/CPU by PCIe (usually four lanes), and part of the southbridge functionality is to act as a PCIe fanout switch. And the terms "northbridge" and "southbridge" have fallen out of common use, largely because the northbridge being on the CPU die was standard practice for both Intel and AMD for over a decade. DDR5 is coming, with the significant change of splitting a DIMM into two separate 32-bit memory channels rather than one 64-bit channel. That allows doubling bandwidth again without the burst length becoming longer than the standard 64-byte cache line size.