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> I had to move SSD cards around so they'd use separate PCIe root complexes to avoid a PCIe <-> CPU data transfer bottleneck I am doing similar things. Have yo
by 1996 6y ago
> I had to move SSD cards around so they'd use separate PCIe root complexes to avoid a PCIe <-> CPU data transfer bottleneck
I am doing similar things. Have you considered looking at how to control by software the PCI lanes assignment?
Intel HSIO seems to be software configurable - except that usually, it's all done just by the bios.
But as PCI specs allow for both device-side and host-side negotiations, it should be doable without "moving SSDs around"
> The throughput differs depending on which specific CPU cores happen to run the processes doing I/Os against different SSDs.
That strikes me as odd. I would check the detail of the PCI lanes and their routing. You could have something funky going on. My first guess would be that it's slow on one core because it's also handling something else, by design or by accident.
There're some bad hardware designs out there. But thanks to stuff like HSIO, it should now be possible to fix the worst ones by software (how else would the bios do it otherwise!) just like in the old days of isapnptools!
- tanelpoder 6y agoAs this is an AMD machine - and as it's a workstation, not server, perhaps this is why they've restricted it in BIOS. I'm not too much of an expert in PCI express - but if this workstation has 4 PCIe root complexes/host bridges, each capable of x32 PCIe 4.0 lanes - and there are no multi-root PCIe switches, wouldn't a lane physically have to communicate with just one PCIe root complex/CPU "port"?
- 1996 6y agoIn theory yes. In practice many things can be different. Carefully check what's happening under the hood. Hopefully, manual configuration of the PCIe will become more commonplace, as most bioses are badly broken each in their own unique way - and unfixable.