There are a couple of FIFO "mailboxes" and spinlock registers between the two cores - I imagine they expect most of the synchronization to happen via that. It i

There are a couple of FIFO "mailboxes" and spinlock registers between the two cores - I imagine they expect most of the synchronization to happen via that. It is a bit weird of a configuration though - is this the first dual core M0+? Does it count as SMP?