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The Cortex-M0 instruction set has some rather unfortunate limitations [1] that can make it difficult for compilers to generate good code for shared/concurrent d

by ohazi 6y ago

The Cortex-M0 instruction set has some rather unfortunate limitations [1] that can make it difficult for compilers to generate good code for shared/concurrent data structures. I can understand why they took this route on a first silicon project, but I hope to see a CM3/4 core or maybe even a riscv core in the near future. [1] https://twitter.com/bitshiftmask/status/1337944590251331584?s=19 https://twitter.com/bitshiftmask/status/1337944590251331584?...

unwind 6y ago
This is a very minor nit, but it's actually a Cortex-M0+ (the plus is significant). Unfortunately the tweet you referenced got that right, so the criticism still stands. See [1] for a short description. I think I knew that the M0+ lacks the regular load/store exclusive instructions from larger ARMs, handy for implementing synchronization primitives ... odd that they've build a dual core then? No idea how that is supposed to work, but haven't checked the docs either. Edit: After browsing the (very nice-looking) RP2040 documents, it seems the only atomic thing on the chip is the special "ghosted" I/O access. That will probably be co-opted to implement atomic data structures, but then it will be at the cost of making access to the actual peripheral whose registers are being "stolen" harder or impossible. Strange, hopefully I'm missing something obvious. :) Also, the PIO peripherals seem awesome! Can't wait to see all the cool things people will pull off with those. The document mentions them being capable of DVI and VGA signalling, even. [1] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M0+ https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M0+
- TD-Linux 6y ago
  There are a couple of FIFO "mailboxes" and spinlock registers between the two cores - I imagine they expect most of the synchronization to happen via that. It is a bit weird of a configuration though - is this the first dual core M0+? Does it count as SMP?
pantalaimon 6y ago
Just disable interrupts while accessing shared data, it's two instructions and the critical section should not be long.
- alexhutcheson 6y ago
  It has two cores, so I don’t believe disabling interrupts would be sufficient unless you’re only using one core.

by ohazi 6y ago

unwind 6y ago

This is a very minor nit, but it's actually a Cortex-M0+ (the plus is significant). Unfortunately the tweet you referenced got that right, so the criticism still stands. See [1] for a short description. I think I knew that the M0+ lacks the regular load/store exclusive instructions from larger ARMs, handy for implementing synchronization primitives ... odd that they've build a dual core then? No idea how that is supposed to work, but haven't checked the docs either. Edit: After browsing the (very nice-looking) RP2040 documents, it seems the only atomic thing on the chip is the special "ghosted" I/O access. That will probably be co-opted to implement atomic data structures, but then it will be at the cost of making access to the actual peripheral whose registers are being "stolen" harder or impossible. Strange, hopefully I'm missing something obvious. :) Also, the PIO peripherals seem awesome! Can't wait to see all the cool things people will pull off with those. The document mentions them being capable of DVI and VGA signalling, even. [1] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M0+ https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M0+

TD-Linux 6y ago
There are a couple of FIFO "mailboxes" and spinlock registers between the two cores - I imagine they expect most of the synchronization to happen via that. It is a bit weird of a configuration though - is this the first dual core M0+? Does it count as SMP?

pantalaimon 6y ago

Just disable interrupts while accessing shared data, it's two instructions and the critical section should not be long.

alexhutcheson 6y ago
It has two cores, so I don’t believe disabling interrupts would be sufficient unless you’re only using one core.