4 ms·
What instructions from an extended ISA are you referring to? The only ones I've seen written up have been: 1. Instructions to change the memory ordering mode,
by alexhutcheson 6y ago
What instructions from an extended ISA are you referring to? The only ones I've seen written up have been:
1. Instructions to change the memory ordering mode, which allows Rosetta2 to skip some expensive memory fences when translating x86 binaries to ARM.
2. Some instructions for matrix math.
I wouldn't expect either of these to affect typical usage or battery life much, unless your workflow involves running things that do a ton of matrix math.
- my123 6y agoAnd the former isn't even an instruction, set a single bit in ACTLR_EL1 and off you go. The second is an extension that talks to a coprocessor that's quite application specific. And that has an unstable ISA that changes every year. Probably not the biggest priority for anyone.
- saagarjha 6y agoWell, four bits: in addition ACTLR_EL1_EnTSO to the kernel also sets ACTLR_EL1_EnAPFLG | ACTLR_EL1_EnAFP | ACTLR_EL1_EnPRSV, whatever those are.
- glitchc 6y agoWow, I guess Torvalds himself must be wrong then: https://arstechnica.com/gadgets/2020/11/__trashed-6/ https://arstechnica.com/gadgets/2020/11/__trashed-6/
- alexhutcheson 6y agoIn that article, Torvalds specifically says: "The main problem with the M1 for me is the GPU and other devices around it" That's a separate issue than the ISA extensions, which apply to the ARM CPU.