Whilst you can easily point your synthesis tool at a new cell library (this is the tool that takes the hardware description in a language like Verilog and produ

Whilst you can easily point your synthesis tool at a new cell library (this is the tool that takes the hardware description in a language like Verilog and produces a circuit that implements it) there is significant back-end work in getting the best out of any library. Intel will probably have to rework their layouts, deal with new memory compilers that have produce memories with different characteristics and adapt memory interfaces that what they need. Their implementation engineers will take time to understand all of the new design rules, quirks and best optimisation strategies that come with an entirely new library (given this is an entirely different fab there could be significant differences). I suspect that's why they're going for Core i3 first, they can get away without lots of detailed work and optimisation to really push the process. A straight-forward (ish) port what you've got and see how it goes will be good enough and will give their implementation engineers experience with the new library that they can then use to work on the higher end.