4 ms·
Cool, how is RISC-V dealing with this? Can’t wait to see what processor in 10 years or so on 1nm lithography look like, they might even be able to run a JavaScr
by andy_ppp 6y ago
Cool, how is RISC-V dealing with this? Can’t wait to see what processor in 10 years or so on 1nm lithography look like, they might even be able to run a JavaScript test suit at a reasonable pace or compile Rust fast :-)
- xiphias2 6y agoIt has an instruction set where the instructions are independent of the size of the register. It's easier to look some videos about it on YouTube than to explain it actually.
- rrss 6y agoGenerally the idea is to make the instruction set "scalable," such that if the CPU's vector ALU doubles in width, applications don't need to be rewritten or recompiled to benefit. (In contrast to existing SIMD instructions, which are for a specific width, which is why e.g. Intel introduces new instructions for wider and wider vectors - AVX1, AVX2, AVX512). ARM and RISC-V are both pursuing this approach, with SVE and the V extension, respectively. Though it is unlikely that vector instructions will help very much for typical JS or compilation workloads.
- ithkuil 6y agoDoes any of these new vector instruction sets that only differ from the previous one fir the width of the operands still allow for a new patient to be filed?
- rrss 6y agoI would guess yes, but don't really have any idea. To clarify, though, the changes introduced in newer SIMD extensions are rarely just a width increase. AVX-512, for example, increased the width from 256-bit to 512-bit, but also brought some substantial programmability improvements.
- xiphias2 6y agoMaybe it's true, but as it can decrease the clock rate, I would never use it, because it completely destroys the predictability of runtime. Linus was quite angry about it for a good reason.