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I wrote SiFive CPUs, not RISC-V there. (because this BeagleV board uses SiFive) There's a _huge_ gap between academic implementations and ones that are actuall
by my123 6y ago
I wrote SiFive CPUs, not RISC-V there. (because this BeagleV board uses SiFive)
There's a _huge_ gap between academic implementations and ones that are actually worth shipping. I can see RISC-V winning quite handily for microcontrollers. But on anything bigger than that...
- dkjaudyeqooe 6y agoPeople said that about open source compilers. Where are we now? You need to give it a few years before you write it off. It's significant that most CS/EE students are now learning the RISC-V architecture.
- brucehoult 6y agoWestern Digital's open sourced SweRV cores are approximately the same performance as the closed-source SiFive 7-series ones. The main difference is the WD cores are 32 bit, no MMU, probably DTIM rather than cache (not sure). The guts of the dual issue decode, register file, pipeline is there, which is the hard part. The other bits could be relatively easily added by the open source community, probably cribbing components from RocketChip.