This is probably because the RAM is internal to the FPGA: > A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA. I'd guess the CPU itself wo

This is probably because the RAM is internal to the FPGA: > A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA. I'd guess the CPU itself would easily fit into an iCE40 (given that RISC-Vs are fitting and the J1 should be simpler) with the RAM external. Several of the iCE40 boards have external RAMs