3 ms·
I'm making a naive guess here. No, superconducting transistors are probably harder to create than non super conducting transistors so the limits on die size fro
by undersuit 6y ago
I'm making a naive guess here. No, superconducting transistors are probably harder to create than non super conducting transistors so the limits on die size from defects are even more pronounced and superconducting doesn't change the speed of light for electrons on the chip so it doesn't change the timing issues arising from large dies.
- akiselev 6y agoThe limits on die size for the competitive consumer chip market are nothing like that of the B2B market. Largest chip ever made was over 40,000 mm^2 [1] compared to Intel's 10900K at ~205 mm^2. In production mainframe chips like IBM's Z15s are on the order of 700mm^2. The fab process has a lot of levers so very low defect rates are possible but not at the scale of a consumer CPU. [1] https://techcrunch.com/2019/08/19/the-five-technical-challenges-cerebras-overcame-in-building-the-first-trillion-transistor-chip/?utm_campaign=fullarticle&utm_medium=referral&utm_source=inshorts https://techcrunch.com/2019/08/19/the-five-technical-challen... Edit: I assume a supercoducting microprocessor would use a strategy similar to the AI monolith in [1]. Just fuse off and route around errors on a contiguous wafer and distribute the computation to exploit the dark zones for heat dissipation.