2 ms·
On first generation Ryzen AVX2 instructions were executed as 2 AVX instructions as the AVX pipeline was 128 bits wide. This was fixed in Zen 2 and nowadays we a
by karavelov 6y ago
On first generation Ryzen AVX2 instructions were executed as 2 AVX instructions as the AVX pipeline was 128 bits wide. This was fixed in Zen 2 and nowadays we are at Zen 3.