3 ms·

I’m having trouble following - can you post a code example?

• Majromax 6y ago
  This has been in the news again lately with Apple Silicon. The ARM architecture has a weaker memory model than x86 in that it does not normally provide "total store ordering". Under that memory model, if thread A executes (from an initially zeroed heap): a = 1; b = 1; then thread B can safely execute: if (b == 1) assert(a == 1); if (a == 0) assert(b == 0); x86 provides this guarantee, but ARM does not -- thread B might see the b=1 write before the a=1 write. Apple Silicon has a runtime toggle (https://old.reddit.com/r/hardware/comments/i0mido/apple_silicon_has_a_runtime_toggle_for_tso_to/ https://old.reddit.com/r/hardware/comments/i0mido/apple_sili...) to provide for that behaviour, which greatly improves performance of translated x86 code (i.e. the translator does not need to insert precautionary memory barriers).
  • KMag 6y ago
    > if (a == 0) assert(b == 0); Even on x86, you can't make this assertion without any synchronization primitives (mutexes, etc.). Without synchronization, the a = 1; b = 1; can run between the (a == 0) and assert(b == 0).
    • Majromax 6y ago
      Ah, of course you're right. I added that line as a bit of an afterthought and meant for it to be atomic, but of course it isn't. Unthinking parallelism is pitch black, and you are likely to be eaten by a grue.