I'm on the other side. I think ARM ignoring their ultra-successful Thumb2 -- which basically made the company --when designing Aarch64 was a huge mistake. Pret

I'm on the other side. I think ARM ignoring their ultra-successful Thumb2 -- which basically made the company --when designing Aarch64 was a huge mistake. Pretty much every embedded RISC-V user values the C extension highly, and many even think it doesn't go far enough because it leaves out things such as push/pop multiple resulting in the code being 3% or 5% bigger than Thumb2 code (but much smaller than anything else in current use). Hence there is a working group creating an optional extension including things like that, based on a customer extension Huawei have already deployed in the field. Having both 2 and 4 byte instruction lengths is a little harder to deal with than having only 4 byte instructions, but it's obviously far easier than having anything from 1 byte to 15 bytes. If you really don't want to do it then you're free to build a CPU without the C extension. All the tools support that. You just need to compile the software you need yourself -- or join a community of like-minded people. Similarly if you want to modify ld to have an option to avoid instructions crossing 32 or 64 byte boundaries (configurable) then that's both pretty easy and I'm sure would also be accepted upstream. You wouldn't need to pad with a NOP or anything like that -- just leave one instruction in uncompressed form.