I think the 5% can maybe be accounted for by the cache line (you mentioned this above, and I don't think the experiment does anything to prevent the issue)? If

I think the 5% can maybe be accounted for by the cache line (you mentioned this above, and I don't think the experiment does anything to prevent the issue)? If it's 1/16th chance of crossing the cache line, that maybe is about 5% of the time? I say that with pretty low confidence though I think you raise a good question, though -- what really is going on here? Is this just a missed optimization compiling for the m1? Or is it actually something fundamental about how reads happen with an m1? I'm definitely not knowledgeable enough to know how to answer this