A related thing that's been on my mind lately is the movement from DDR4 to DDR5, and what that means for ECC. DDR4 and previous generations use 64-bit channels,

A related thing that's been on my mind lately is the movement from DDR4 to DDR5, and what that means for ECC. DDR4 and previous generations use 64-bit channels, which needs 8 bits for SECDED protection; so ECC-supporting DIMMs are 72 bits wide. DDR5 goes to (twice as many) 32-bit channels, though, which need 7 bits for SECDED protection -- but DRAM dice are traditionally made in multiples of 8-bit widths, so DDR5 ECC-supporting DIMMS are 80 bits wide (two 40-bit channels). What's interesting about this is that there's an extra bit of (ECC-protected) physical memory available to the hardware for each 32-bit word, at zero cost for a machine that already requires ECC. This raises some interesting opportunities, like tagged memory, that I haven't seen explored anywhere yet.