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Good question, and the answer is still a matter of opinion. I think the HN crowd is mostly excited because it is an ISA that fits two important criteria: * Yo
by meekrohprocess 6y ago
Good question, and the answer is still a matter of opinion.
I think the HN crowd is mostly excited because it is an ISA that fits two important criteria:
* You can build a RISC-V CPU into your own digital designs for $0. There are also a lot of free designs which use open-source buses like Wishbone if you don't want to build your own.
* Linux/GCC/etc. will probably support a compliant RISC-V implementation.
And the cynical/realist crowd is harrumph-ing after a few important questions, like:
* Many important features are not yet finalized, including things as basic as a nested interrupt controller. So, how compatible will modern RISC-V implementations be with future software?
* Will "good enough" performance actually be good enough? It's still not clear whether a RISC-V CPU will be competitive with ARM et al on power and performance on a similar process node. It might be, but the ecosystem needs to mature.
So it's one of those things that always seems to be 5 years away, like practical fission or the year of the Linux desktop.
But if we ever do get to a point where you can use something like LiteX to generate a RISC-V SoC with N CPUs and driver support for its major peripherals on Linux, that would be exciting. Fabrication on 45-130nm process nodes might also be affordable for small startups by that point, too.
- nickik 6y agoNr.1 reason is that you need a open ISA in order to have an open processor. Therefore you can only have proper OpenHardware movement with an open processor. The RISC-V foundation was only created in 2015 before that it was basically a research project so saying anything RISC-V related is 'always' 5 years away is a strange statement. And I also don't know where you get 'good enough', RISC-V is not a processor, its and ISA and we know that ISA have relatively little impact implementation speeds. We already have RISC-V processors at the same node as ARM processors that beat them in many criteria.
- astrange 6y ago> we know that ISA have relatively little impact implementation speeds But this is not true, decoders cannot make up for everything. ISAs can also do a lot to improve software security, not to mention ease of use. RISC-V is just not well designed. Though it might be good enough… https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d99...
- nickik 6y agoPerformance is not one thing, we have processors from so small they can almost not be seen to gigantic AI chips. RISC-V made some design choices and some people like some of them and some people don't like others, just like with anything else in the world. Christopher Celio as part of his PhD did ISA comparison and found no way that RISC-V is systematically worse, in fact in many situations its better. David A Patterson, Dave Ditzel and many other long time engineers in this space seem to really like it. And btw, you could make a much longer The Good, The Bad, The Ugly list about ARM as well. By that definition no ISA is well designed.
- brucehoult 6y agoThat's the opinion of one ARM engineer I've never heard of. Here's the opinion of probably THE most important ARM engineer of the 1990s and 2000s, Dave Jaggar who developed the ARM7TDMI, Thumb, Thumb2. https://www.youtube.com/watch?v=_6sh097Dk5k https://www.youtube.com/watch?v=_6sh097Dk5k Check at 51:30 where he says "Are there any ARM snipers? No ... I would Google RISC-V and find out all about it. They've done a fine instruction set, a fine job [...] it's the state of the art now for 32-bit general purpose instruction sets. And it's got the 16-bit compressed stuff. So, yeah, learning about that, you're learning from the best."
- astrange 6y agoDid he also design AArch64? Because I've noticed it can be used to design very fast processors, yet abandons most decisions in ARM7 and Thumb. I was just curious about how SIMD worked in RISC-V so I looked it up… and apparently RISC-V doesn't have SIMD, instead it brings back microcoded large vector operations from the 70s, and the RISC-V designers called SIMD bad and compared it to the opioid crisis because it means there are too many instruction opcodes? https://www.sigarch.org/simd-instructions-considered-harmful/ https://www.sigarch.org/simd-instructions-considered-harmful... So I'm now even less impressed and also slightly offended. This is not realistic, short vectors are important and easy to do in hardware.
- nickik 6y ago
- zucker42 6y agoIsn't fission already practical?
- meekrohprocess 6y agoMaybe. I'll believe it when a large-ish city runs off of it.
- mlyle 6y agoI mean, France and Japan got 70% of their power from it not too many years ago...
- maelito 6y agoThe author probably meant fusion. 70% of France's electricity comes from fission, but that's only electric power.
- meekrohprocess 6y agoYeah, that - thanks. I'm not a nukular physicist.