2 ms·

I think 5% is a non-trivial difference but alright, its a much bigger difference on the M1. I guess I still don't understand whats going on here. Scenario 1 h

by jayd16 6y ago

I think 5% is a non-trivial difference but alright, its a much bigger difference on the M1. I guess I still don't understand whats going on here. Scenario 1 has two spatially close reads followed by two dependent random access reads. Scenario 3 (2+) has two spatially close reads, and two pairs of dependent random access reads of two spatially close locations. Why does it follow that this is caused by a change in memory access concurrency? The two required round trips should dominate both on the M1 and an Intel but for some reason the M1 performs worse than that. Why? I can't help but feel the first snippet triggers some SIMD path while the 3rd snippet fails to.

wrsh07 6y ago
I think the 5% can maybe be accounted for by the cache line (you mentioned this above, and I don't think the experiment does anything to prevent the issue)? If it's 1/16th chance of crossing the cache line, that maybe is about 5% of the time? I say that with pretty low confidence though I think you raise a good question, though -- what really is going on here? Is this just a missed optimization compiling for the m1? Or is it actually something fundamental about how reads happen with an m1? I'm definitely not knowledgeable enough to know how to answer this