FPGAs are frequently not connected with a dedicated CPU at all, and even when they are they may be connected over a link with lower bandwidth/higher latency tha

FPGAs are frequently not connected with a dedicated CPU at all, and even when they are they may be connected over a link with lower bandwidth/higher latency than you would like. In these cases you usually have a bunch of management and logic tasks which are better suited to a CPU (basically anything with a large number of different serial steps and complex control flow will probably synthesize poorly directly to an FPGA: this is probably what the authors described as 'too complex for dedicated hardware'), so you synthesize a CPU in the FPGA fabric which usually has a direct memory map to whatever registers you need in the FPGA design to accomplish your goals. This is common enough basically every FPGA vendor also sells FPGA SOCs which have a hard CPU attached to the fabric, and if you are using one of those then you will generally not synthesize a CPU in the fabric because it'll usually be slower and less power efficient than the hard CPU you have. But that CPU also isn't free and if your CPU compute requirements are not particularly high than the soft CPU might be more efficient for your usecare (or a hard CPU may not be an option in the range you need).