2 ms·
That's not really the same thing though. Those are just different caches of RAM. There's nothing really special about them.
by jimktrains2 6y ago
That's not really the same thing though. Those are just different caches of RAM. There's nothing really special about them.
- angry_octet 6y agoIt's exactly Harvard. Instructions can only be loaded from the I cache, and data operands from the D cache. If you JIT something you have to flush the relevant D cache entries and invalidate the relevant I cache and then it will get reloaded.
- jimktrains2 6y agoIt appears this is called a modified Harvard architecture. I wasn't aware of that. https://en.m.wikipedia.org/wiki/Harvard_architecture https://en.m.wikipedia.org/wiki/Harvard_architecture https://en.m.wikipedia.org/wiki/Modified_Harvard_architecture https://en.m.wikipedia.org/wiki/Modified_Harvard_architectur...
- angry_octet 6y agoYes. Linear address spaces are an abstraction to hide this, because everything is in pages (minimum 4k on most machines, up to huge page sizes), and it is the pages that are controlled in terms of W^X. In the era of ROP and gadgets (control flow being determined by data, to implement strange virtual machine and interpreters) it seems somewhat quaint, but it has made exploits a lot more complicated. The mixing of JMP/RET addresses and stack data is why stack overflow and ROP is so easy; CFG, CET and shadow stacks are all trying to achieve separate I and D stacks.