3 ms·
RV32IM, 2.04 DMIPS/MHz, 95.3 MHz, 15K LUTs, 8K LUT FFs, 6 BRAMs on Zynq 7020. I'm curious if this will work on Lattice ECP5- I'm not really sure if Synplify su
by jhallenworld 6y ago
RV32IM, 2.04 DMIPS/MHz, 95.3 MHz, 15K LUTs, 8K LUT FFs, 6 BRAMs on Zynq 7020.
I'm curious if this will work on Lattice ECP5- I'm not really sure if Synplify supports system verilog to the same degree as the Xilinx tools. ECP5 is interesting because it's a $10 FPGA..
- mhh__ 6y agoAt a glance I think it would fit although I might be thinking of the bigger ECP5s which are in the same price bracket as some Zynqs
- mithro 6y agoFWIW Google is working on improving the support for SystemVerilog in open source tools. On the developer tooling side, there is https://github.com/google/verible https://github.com/google/verible for linting, code formatting and code indexing. On the actual compilation side with there are https://github.com/alainmarcel/Surelog https://github.com/alainmarcel/Surelog and https://github.com/alainmarcel/UHDM https://github.com/alainmarcel/UHDM which are then being coupled with open source tools like Yosys to allow targeting Xilinx 7 Series and Lattice ECP5 FPGA ICs with fully open source flows using fully open source FPGA tools like symbiflow.github.io