5 ms·

This reminds me of the Harvard architecture: https://en.wikipedia.org/wiki/Harvard_architecture https://en.wikipedia.org/wiki/Harvard_architecture Perhaps mos

This reminds me of the Harvard architecture: https://en.wikipedia.org/wiki/Harvard_architecture https://en.wikipedia.org/wiki/Harvard_architecture Perhaps most familiar to the typical HN reader via Arduinos, and contrasted with von Neumann: https://en.wikipedia.org/wiki/Von_Neumann_architecture https://en.wikipedia.org/wiki/Von_Neumann_architecture And anyone who has tried to make any kind of interesting general-purpose system on a Harvard design will tell you that it's not really practical.

angry_octet 6y ago
Except for the many CPUs with separate instruction and data caches, i.e. Harvard architecture L1, von Neumann main memory. https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/caches-and-self-modifying-code https://community.arm.com/developer/ip-products/processors/b...
- jimktrains2 6y ago
  That's not really the same thing though. Those are just different caches of RAM. There's nothing really special about them.
  - angry_octet 6y ago
    It's exactly Harvard. Instructions can only be loaded from the I cache, and data operands from the D cache. If you JIT something you have to flush the relevant D cache entries and invalidate the relevant I cache and then it will get reloaded.
    - jimktrains2 6y ago
      It appears this is called a modified Harvard architecture. I wasn't aware of that. https://en.m.wikipedia.org/wiki/Harvard_architecture https://en.m.wikipedia.org/wiki/Harvard_architecture https://en.m.wikipedia.org/wiki/Modified_Harvard_architecture https://en.m.wikipedia.org/wiki/Modified_Harvard_architectur...
      - angry_octet 6y ago
        Yes. Linear address spaces are an abstraction to hide this, because everything is in pages (minimum 4k on most machines, up to huge page sizes), and it is the pages that are controlled in terms of W^X. In the era of ROP and gadgets (control flow being determined by data, to implement strange virtual machine and interpreters) it seems somewhat quaint, but it has made exploits a lot more complicated. The mixing of JMP/RET addresses and stack data is why stack overflow and ROP is so easy; CFG, CET and shadow stacks are all trying to achieve separate I and D stacks.
jimktrains2 6y ago
Arduinos and the like can jump to ram and execute code from it. They simply also have a read-only portion of memory where the code is stored. You can also treat the ROM as memory and use it to store tables, saving you from having to use RAM for them.

angry_octet 6y ago

Except for the many CPUs with separate instruction and data caches, i.e. Harvard architecture L1, von Neumann main memory. https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/caches-and-self-modifying-code https://community.arm.com/developer/ip-products/processors/b...

jimktrains2 6y ago
That's not really the same thing though. Those are just different caches of RAM. There's nothing really special about them.
- angry_octet 6y ago
  It's exactly Harvard. Instructions can only be loaded from the I cache, and data operands from the D cache. If you JIT something you have to flush the relevant D cache entries and invalidate the relevant I cache and then it will get reloaded.
  - jimktrains2 6y ago
    It appears this is called a modified Harvard architecture. I wasn't aware of that. https://en.m.wikipedia.org/wiki/Harvard_architecture https://en.m.wikipedia.org/wiki/Harvard_architecture https://en.m.wikipedia.org/wiki/Modified_Harvard_architecture https://en.m.wikipedia.org/wiki/Modified_Harvard_architectur...
    - angry_octet 6y ago
      Yes. Linear address spaces are an abstraction to hide this, because everything is in pages (minimum 4k on most machines, up to huge page sizes), and it is the pages that are controlled in terms of W^X. In the era of ROP and gadgets (control flow being determined by data, to implement strange virtual machine and interpreters) it seems somewhat quaint, but it has made exploits a lot more complicated. The mixing of JMP/RET addresses and stack data is why stack overflow and ROP is so easy; CFG, CET and shadow stacks are all trying to achieve separate I and D stacks.

jimktrains2 6y ago

Arduinos and the like can jump to ram and execute code from it. They simply also have a read-only portion of memory where the code is stored. You can also treat the ROM as memory and use it to store tables, saving you from having to use RAM for them.