There are tons of people using System Verilog for RISC-V. The majority of work done is with System Verilog and not Chisel. Having lots of cores in both Chisel,

There are tons of people using System Verilog for RISC-V. The majority of work done is with System Verilog and not Chisel. Having lots of cores in both Chisel, System Verilog and many other languages (VHDL,BlueSpec and so on) is a huge benfit for RISC-V SiFive values programmability above everything and for that Chisel is pretty clearly an advantage.