It seems broadly comparable to an ARM Cortex A9 in width and reorder depth but it seems to be using a lot more pipeline stages to do that. Probably that's beca

It seems broadly comparable to an ARM Cortex A9 in width and reorder depth but it seems to be using a lot more pipeline stages to do that. Probably that's because they had less engineer-years to invest in the design than ARM did. It looks like it's using pure automatic synthesis so the clock speed will tend to be lower on equivalent process nodes too. The big question is how accurate the prefetcher and branch predictors are. It's entirely possible for an 2 issue out of order core to be slower than 2 issue in order core if the later is significantly better at speculating. Still, that's a good bit of work they should be proud for putting out there and I hope other people build on it. EDIT: Oh, wait, they don't mention register renaming. Hmm, well, I guess no speculating over multiple iterations of a loop then. EDIT2: No, the PDF the link mentions a rename unit. http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...