My understanding of these RISC-V vector instructions is that they're limited to a vector register, which probably won't be too big, perhaps 512-bits or so. Comp

My understanding of these RISC-V vector instructions is that they're limited to a vector register, which probably won't be too big, perhaps 512-bits or so. Compared to the cost of a context switch, the cost of finishing the current instruction should be negligible.