I wrote a small blog post about using netlistsvg, yosys, and ghdl to make block diagrams for VHDL here: https://nobodywasishere.github.io/netlistsvg/ https://no

I wrote a small blog post about using netlistsvg, yosys, and ghdl to make block diagrams for VHDL here: https://nobodywasishere.github.io/netlistsvg/ https://nobodywasishere.github.io/netlistsvg/