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I often find it easier to grok things like circuits and logic visually, certainly when in circuit design/PCB mode. Does anyone know of any open source software
by PoachedSausage 6y ago
I often find it easier to grok things like circuits and logic visually, certainly when in circuit design/PCB mode.
Does anyone know of any open source software for taking smallish chunks of Verilog/VHDL and making a visual representation/schematic?
- minetest2048 6y agoyosys with yosys show command can do it for Verilog: http://www.clifford.at/yosys/files/yosys_appnote_011_design_investigation.pdf http://www.clifford.at/yosys/files/yosys_appnote_011_design_... I found it really helpful to see what a chunk of Verilog code would look like after synthesis. There is an online version at here: http://www.clifford.at/yosys/nogit/YosysJS/snapshot/demo02.html http://www.clifford.at/yosys/nogit/YosysJS/snapshot/demo02.h... which uses YosysJS. Hopefully someone can port Compiler Explorer UI to this
- mhh__ 6y agohttps://digitaljs.tilk.eu/ https://digitaljs.tilk.eu/ also this
- PoachedSausage 6y agoI had a feeling yosys might do it somehow. Thanks.
- deleted 6y ago[deleted]
- nobodywasishere 6y agoI wrote a small blog post about using netlistsvg, yosys, and ghdl to make block diagrams for VHDL here: https://nobodywasishere.github.io/netlistsvg/ https://nobodywasishere.github.io/netlistsvg/
- PoachedSausage 6y agoThanks. Very useful.