I think the memory just provides additional storage bits to detect the issue, but doesn't contain the logic. This is in line with all technical parameters of D

I think the memory just provides additional storage bits to detect the issue, but doesn't contain the logic. This is in line with all technical parameters of DRAM: everything must be as cheap as possible, and all the difficult parts are moved to the memory controller. Which is the right thing to do, because you can share one memory controller with multiple DRAM chips.