> However, in hardware this model could be made clockless / asynchronous I know you didn't imply otherwise, but it's worth pointing out that ternary logic is b

> However, in hardware this model could be made clockless / asynchronous I know you didn't imply otherwise, but it's worth pointing out that ternary logic is by no means required for asynchronous hardware design. The same effect is possible with dual rail channels using two wires per bit, or even fewer on average using Sperner codes and the like. > computations go as fast as they can Although asynchronous circuits might not have to wait for a clock, they do have to wait for handshake completion detection in various forms. It's more like a trade-off than a free lunch.