3 ms·

> elegant foundation for computation. -1, 0, +1 has as elegant symmetry that will inspire fascination until either someone can prove its inferiority with some

> elegant foundation for computation. -1, 0, +1 has as elegant symmetry that will inspire fascination until either someone can prove its inferiority with some heretofore unimagined model of computing or someone builds a clearly superior device based on it. I strongly doubt such a device is possible with contemporary two dimensional etched semiconductors; too many people have been torturing conventional mosfet circuits for too many decades to think they've left much on the table. But who knows what the future will deliver? Maybe we'll start computing with proteins next year and somehow 3 (or more) levels will make sense.

drran 6y ago
If we use third state as "spacer", then we will be able to use every single line connection as serial connection, thus massively parallel, clock-less logic will be possible. Instead of clocked design: data0: 000001111111111111111111111111111000000000 data1: 000000000000000000000000000000000000000000 data2: 000111111111111111111111111111100000000000 ... clock: 000000000001111111111100000000000000000000 We will be able to use clockless design: data0: --111--- data1: ---000-- data2: ----111- Or even: data: --111---000---111--- (1 represents high signal, 0 - low signal, - - neutral signal).
- jan6 6y ago
  I'd upvote thrice if I could ;) there's so many ways to utilize ternary, on different levels, you could use this kind of ternary hardware serialisation as an addon to normal binary stuff, not only base-3 computing, for example if -1 is the "empty" then I'd imagine it'd make it trivial to interface with, and emulate binary systems (so a ternary cpu would not need take a hit for binary emulation, only the architecture), which could be the gateway to get people interested in it initially, without needing 100% new everything, etc... just my uneducated guess tho...

drran 6y ago

If we use third state as "spacer", then we will be able to use every single line connection as serial connection, thus massively parallel, clock-less logic will be possible. Instead of clocked design: data0: 000001111111111111111111111111111000000000 data1: 000000000000000000000000000000000000000000 data2: 000111111111111111111111111111100000000000 ... clock: 000000000001111111111100000000000000000000 We will be able to use clockless design: data0: --111--- data1: ---000-- data2: ----111- Or even: data: --111---000---111--- (1 represents high signal, 0 - low signal, - - neutral signal).

jan6 6y ago
I'd upvote thrice if I could ;) there's so many ways to utilize ternary, on different levels, you could use this kind of ternary hardware serialisation as an addon to normal binary stuff, not only base-3 computing, for example if -1 is the "empty" then I'd imagine it'd make it trivial to interface with, and emulate binary systems (so a ternary cpu would not need take a hit for binary emulation, only the architecture), which could be the gateway to get people interested in it initially, without needing 100% new everything, etc... just my uneducated guess tho...