3 ms·
Modern FPGAs do it pretty much the same -- there are high and low drivers, and one of them gets activated at a time. Note that this link is tri-state, not tern
by theamk 6y ago
Modern FPGAs do it pretty much the same -- there are high and low drivers, and one of them gets activated at a time.
Note that this link is tri-state, not ternary. The "tri-state" is still binary, the third state is to allow attaching multiple outputs to the same bus. Or in the C pseudocode:
Regular binary:
enum { FALSE, TRUE } value;
value = result()
Ternary:
enum { UNKNOWN, FALSE, TRUE } value;
value = result()
Tri-state (as Z80 and every modern computer does it):
enum { FALSE, TRUE } value;
if (enabled())
value = result()
(the idea is you might have multiple components driving the same "value", and only one of them should be enabled at a time. Bad things happen if more than one is enabled at a time, or none are)
- tyingq 6y agoThat's helpful, though googling around a bit suggests both the Z80 (and popular peripheral chips) and FPGA/CPLD devices do have non-bus, single pin abstractions that can output and input 3 states with a single pin. But replicating that with an ATMEL or similar generally requires dancing around with resistor ladders or similar.
- theamk 6y agoCan you tell me more about how can Z80 (or popular peripheral chips) "can output and input 3 states with a single pin"? Or maybe give some web links? I am pretty familiar with that chip, so hearing this surprises me. For the output side, I guess I you can tri-state the output, but this will by default keep the previous voltage, you will need some resistors to actually emit a voltage outer than "low" or "high". And Z80 cannot even control this on per-pin basis, since it has no integrated GPIOs. For the input side, I have no idea how would Z80 get more than two states. All the peripherals I know of (like 82C55 GPIO chips) also only provide two input levels as well. The only way to get 3-state input into a system I can think of are: - ADC input followed by software thresholding (this will be pretty slow, and works with hundreds of states, not just 3) - Use external voltage comparators to split a single input wire into multiple input pins. This no long is "single pin" though. - Some FPGA/CPLDs have multiple banks with changeable input thresholds. This lets you avoid external comparators. You'd still need multiple pins for each input wire.
- tyingq 6y agoApologies, you're right. It was my own misreading bits of code where a chip was inferring its own pin state (1/0/hi-z) based on previous calls or flags and what it should be. Not inferring it externally.