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The RISC V position is that compressed instructions with macro ops fusion can solve this issue: https://erik-engheim.medium.com/the-genius-of-risc-v-micropro
by yaantc 6y ago
The RISC V position is that compressed instructions with macro ops fusion can solve this issue:
https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6
We'll see in practice as more powerful RISC V cores are developed and used. For a new architecture like this it's normal to start with deeply embedded (and relatively low power) cores, and then move up the food chain. It takes time to build an ecosystem.
Currently the ISA is minimalist but I assume that at the high end some extensions still in development will eventually become expected, like bit operations or the vector extension.
- neilalexander 6y agoThat’s a very interesting link and overview, thanks!
- alain94040 6y agoI don't think anyone can tell anymore whether an instruction set is superior just with theoretical high-level arguments. The only way the pros know for sure is to model the pipeline, run benchmarks and measure the resulting performance for each variation. That movement started with Computer Architecture: A Quantitative Approach, which is from late 80s/early 90s?
- socialdemocrat 6y agoRead up on Esperanto Technologies mentioned here: https://medium.com/swlh/what-is-innovative-about-risc-v-a821036a1568 https://medium.com/swlh/what-is-innovative-about-risc-v-a821... They use small RISC-V cores with the vector extension to do high performance machine learning. Basically they make minimalist small cores supporting this extension so they can put over 1000 of these cores on one SoC.