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I’ve seen quite a few articles and people lamenting about how RISC-V is a badly designed ISA and requires a lot of instructions to do the same amount of work as

I’ve seen quite a few articles and people lamenting about how RISC-V is a badly designed ISA and requires a lot of instructions to do the same amount of work as other architectures. It would be interesting if someone knowledgeable on this could summarise whether that’s really a problem, or if there’s anything that would make RISC-V a strong or weak proposition?

ranger207 6y ago
>RISC-V... requires a lot of instructions to do the same amount of work as other architectures. So... they're complaining that it's RISC?
- adrian_b 6y ago
  No they are complaining that it is too RISC compared to well designed RISC ISAs, e.g. ARM or POWER.
  - GeorgeTirebiter 6y ago
    Do, please, look at The RISC-V Reader: An Open Architecture Atlas (book). There, ARM and x86 are directly compared with RISC-V. It would appear calling ARM 'well-designed' is an error. Calling it 'market success' is accurate. I've been on the RV bandwagon for five years now, and yet...as is usual in the corners of any non-trivial subsystem (arch; compiler; web environment; you name it), sticky unpleasant (even ugly) details emerge. For example, in RISC-V, the bits are 'jumbled up' when encoding constants; the argument is it, ultimately, makes the processing faster (due to the way sign-extension works). And, yes, this sort of detail is swept away into a debugger or other tools, so practically, no big deal. And yet... classic archs like pdp-11 don't have this problem. (it has other performance problems). And recently, RV supports big endian. Why? I don't know. What is happening is what happens when you get too many cooks: exploding complexity for minimal system gain. I'm afraid that RISC-V's time has come and gone. It is a 20th century instruction set attempting to serve us well into the 21st century. In my opinion, I think it's time for a do-over. RISC-VI anyone?
    - meekrohprocess 6y ago
      > For example, in RISC-V, the bits are 'jumbled up' when encoding constants; the argument is it, ultimately, makes the processing faster (due to the way sign-extension works). It's not just sign-extension. You can naïvely gather several immediate bits without knowing what the opcode is, and the source/destination register IDs are also always in the same place. It does help to simplify the digital design, because your decoding logic can pluck out a few fields with no state dependencies. I had the same response to the odd instruction format at first, but it's grown on me over time. >And recently, RV supports big endian. Why? Probably to support networking equipment. They still strongly recommend using little-endian.
    - adrian_b 6y ago
      I was not clear enough by what I meant by "ARM". The traditional 32-bit ARM instruction set is obsolete and it does not matter for any new designs. I was not referring to it. The two modern ARM instruction sets, the 16-bit-encoded ARMv7-M / ARMv8-M (for microcontrollers) and the 64-bit (32-bit-encoded) ARMv8-A, are very different from the traditional ARM ISA and they both are very well designed, incomparably better than RISC-V. RISC-V is primitive even compared to the instructions sets used 50 years ago. It includes a few good ideas and the RISC-V team has the merit of popularizing the fact that the older vector ISAs of the seventies were better than the more recent SIMD ISAs of the nineties, which lead to modern vector ISAs, e.g. the RISC-V vector extension and ARM SVE. However the base RISC-V ISA is extremely weak and its only merit is that it is simple enough to be easy to implement in student projects.
yaantc 6y ago
The RISC V position is that compressed instructions with macro ops fusion can solve this issue: https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6 We'll see in practice as more powerful RISC V cores are developed and used. For a new architecture like this it's normal to start with deeply embedded (and relatively low power) cores, and then move up the food chain. It takes time to build an ecosystem. Currently the ISA is minimalist but I assume that at the high end some extensions still in development will eventually become expected, like bit operations or the vector extension.
- neilalexander 6y ago
  That’s a very interesting link and overview, thanks!
- alain94040 6y ago
  I don't think anyone can tell anymore whether an instruction set is superior just with theoretical high-level arguments. The only way the pros know for sure is to model the pipeline, run benchmarks and measure the resulting performance for each variation. That movement started with Computer Architecture: A Quantitative Approach, which is from late 80s/early 90s?
- socialdemocrat 6y ago
  Read up on Esperanto Technologies mentioned here: https://medium.com/swlh/what-is-innovative-about-risc-v-a821036a1568 https://medium.com/swlh/what-is-innovative-about-risc-v-a821... They use small RISC-V cores with the vector extension to do high performance machine learning. Basically they make minimalist small cores supporting this extension so they can put over 1000 of these cores on one SoC.

ranger207 6y ago

>RISC-V... requires a lot of instructions to do the same amount of work as other architectures. So... they're complaining that it's RISC?

adrian_b 6y ago
No they are complaining that it is too RISC compared to well designed RISC ISAs, e.g. ARM or POWER.
- GeorgeTirebiter 6y ago
  Do, please, look at The RISC-V Reader: An Open Architecture Atlas (book). There, ARM and x86 are directly compared with RISC-V. It would appear calling ARM 'well-designed' is an error. Calling it 'market success' is accurate. I've been on the RV bandwagon for five years now, and yet...as is usual in the corners of any non-trivial subsystem (arch; compiler; web environment; you name it), sticky unpleasant (even ugly) details emerge. For example, in RISC-V, the bits are 'jumbled up' when encoding constants; the argument is it, ultimately, makes the processing faster (due to the way sign-extension works). And, yes, this sort of detail is swept away into a debugger or other tools, so practically, no big deal. And yet... classic archs like pdp-11 don't have this problem. (it has other performance problems). And recently, RV supports big endian. Why? I don't know. What is happening is what happens when you get too many cooks: exploding complexity for minimal system gain. I'm afraid that RISC-V's time has come and gone. It is a 20th century instruction set attempting to serve us well into the 21st century. In my opinion, I think it's time for a do-over. RISC-VI anyone?
  - meekrohprocess 6y ago
    > For example, in RISC-V, the bits are 'jumbled up' when encoding constants; the argument is it, ultimately, makes the processing faster (due to the way sign-extension works). It's not just sign-extension. You can naïvely gather several immediate bits without knowing what the opcode is, and the source/destination register IDs are also always in the same place. It does help to simplify the digital design, because your decoding logic can pluck out a few fields with no state dependencies. I had the same response to the odd instruction format at first, but it's grown on me over time. >And recently, RV supports big endian. Why? Probably to support networking equipment. They still strongly recommend using little-endian.
  - adrian_b 6y ago
    I was not clear enough by what I meant by "ARM". The traditional 32-bit ARM instruction set is obsolete and it does not matter for any new designs. I was not referring to it. The two modern ARM instruction sets, the 16-bit-encoded ARMv7-M / ARMv8-M (for microcontrollers) and the 64-bit (32-bit-encoded) ARMv8-A, are very different from the traditional ARM ISA and they both are very well designed, incomparably better than RISC-V. RISC-V is primitive even compared to the instructions sets used 50 years ago. It includes a few good ideas and the RISC-V team has the merit of popularizing the fact that the older vector ISAs of the seventies were better than the more recent SIMD ISAs of the nineties, which lead to modern vector ISAs, e.g. the RISC-V vector extension and ARM SVE. However the base RISC-V ISA is extremely weak and its only merit is that it is simple enough to be easy to implement in student projects.

yaantc 6y ago

The RISC V position is that compressed instructions with macro ops fusion can solve this issue: https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6 We'll see in practice as more powerful RISC V cores are developed and used. For a new architecture like this it's normal to start with deeply embedded (and relatively low power) cores, and then move up the food chain. It takes time to build an ecosystem. Currently the ISA is minimalist but I assume that at the high end some extensions still in development will eventually become expected, like bit operations or the vector extension.

neilalexander 6y ago
That’s a very interesting link and overview, thanks!
alain94040 6y ago
I don't think anyone can tell anymore whether an instruction set is superior just with theoretical high-level arguments. The only way the pros know for sure is to model the pipeline, run benchmarks and measure the resulting performance for each variation. That movement started with Computer Architecture: A Quantitative Approach, which is from late 80s/early 90s?
socialdemocrat 6y ago
Read up on Esperanto Technologies mentioned here: https://medium.com/swlh/what-is-innovative-about-risc-v-a821036a1568 https://medium.com/swlh/what-is-innovative-about-risc-v-a821... They use small RISC-V cores with the vector extension to do high performance machine learning. Basically they make minimalist small cores supporting this extension so they can put over 1000 of these cores on one SoC.