Typically from an ISA perspective something like - vector length register, to avoid loop epilogues. - scatter-gather and strided memory ops - support for pre

Typically from an ISA perspective something like - vector length register, to avoid loop epilogues. - scatter-gather and strided memory ops - support for predication / masking - looser alignment restrictions, ideally as small as the element size rather than the entire vector width. Look into Arm SVE and RISC-V V extension for modern incantations of this. Though the x86 world is slowly getting closer too.