15 ms·
The original Wirth RISC5 version runs in 1 MB RAM on an ancient Xilinx FPGA board. The RISC-V binaries are a bit larger, but still runs in 1 MB (but more is pos
by johndoe0815 6y ago
The original Wirth RISC5 version runs in 1 MB RAM on an ancient Xilinx FPGA board. The RISC-V binaries are a bit larger, but still runs in 1 MB (but more is possible). A bit too large for typical block RAM sizes of affordable FPGAs, unfortunately.
Some details on the port and the binary size differences can be found in the project report: https://github.com/solbjorg/oberon-riscv/blob/master/report.pdf https://github.com/solbjorg/oberon-riscv/blob/master/report....
- snvzz 6y ago"block ram" (like iCE40's sysMEM) is usually very fast, fancy and dual port, which is why there's so little of it, and is typically spread across the die for reduced latency purposes. From a CPU-in-FPGA perspective, it could be used for e.g. L1 cache. Actual RAM can be slower and external to the FPGA chip. The ULX3S (which can support the minimig Amiga implementation) and the DE10-Nano (miSTer's base board) would make overkill targets for this.
- johndoe0815 6y agoOf course, external RAM is an option. However, using external SDRAM increases the complexity of the hardware significantly, which takes away a bit of the elegance and simplicity of Wirth's original RISC5 FPGA system. Wirth's system used a Xilinx Spartan 3 board with 1 MB of 32 bit wide fast asynchronous SRAM (https://multicores.org/blog/small-is-beautiful.html https://multicores.org/blog/small-is-beautiful.html). Unfortunately, FPGA boards with 32 bit wide SRAM are really hard to find nowadays, especially those supported by SymbiFlow...
- snvzz 6y agoDefinitely. SRAM is pure joy to use, but less and less common in FPGA devboards by the day.
- cfbsoftware 6y agoWe (CFB Software) recently managed to squeeze the full Project Oberon into 512 KB of BRAM on Digilent's Arty7-100T and NexysA7-100T boards. It is sufficient to recompile the entire system on itself.