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> The best DSP coprocessors generally use a VLIW instruction set and no amount of extensions will turn RISC-V into that. Please check P extension. > The bes
by qlk1123 6y ago
> The best DSP coprocessors generally use a VLIW instruction set and no amount of extensions will turn RISC-V into that.
Please check P extension.
> The best graphics coprocessors use a SIMT instruction set and no extension will make RISC-V into that.
Please check V extension.
> Hardware design doesn't have such nice abstraction layers and while IP blocks exist designing one has a certain irreducable cost which won't be reduced that much by using a RISC-V design.
RISC-V is still in its early stage, but all these concerns have been considered seriously. The foundation hosts many different Task Group to tackle all possible needs.
> But the performance penalties of trying to use a general purpose ISA, even one with extensions, are very real and won't be enough to make the savings worthwhile.
Only time will tell.
- Symmetry 6y ago> Please check P extension. That doesn't seem to have anything to do with software scheduled general parallel execution of instructions. Letting you have a branch, an arithmetic operation, and a load in the same instruction for example. > Please check V extension SIMD is not the same as SIMT. SIMT doesn't handle divergent flow control well compared to a general purpose computer. However it does do it better than SIMD, even predicated SIMD, in important ways. I think that trying to come up with one ISA that can handle every use case is liable to be just as successful as coming up with one programming language that can handle every use case.
- brucehoult 6y agoRVV has facilities specifically for handling divergent and convergent SIMT control flow. RVV is an excellent target for code in languages such as CUDA and OpenCL. Yunsup Lee's PhD thesis shows how (using a direct predecessor of RVV).