Could you elaborate on why you think RISC-V is a mediocre instruction-set architecture? I would rather say it is genius: https://erik-engheim.medium.com/the-ge

Could you elaborate on why you think RISC-V is a mediocre instruction-set architecture? I would rather say it is genius: https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6 https://erik-engheim.medium.com/the-genius-of-risc-v-micropr... RISC-V has learned a lot from the mistakes of previous ISAs and made sure the instruction-set fits both low power consumption solution as well as high performance solutions. All sorts of benchmark tests show that RISC-V from a theoretical standpoint would execute programs faster. You can tell this by analysis how how many instructions are needed for different programs for different architectures. And how many clock cycles are needed per instruction etc.