I do wonder if part of Apple's success might just be from accepting a lower clock speed. By allowing more FO4s of wire and gate delay between clock latches you

I do wonder if part of Apple's success might just be from accepting a lower clock speed. By allowing more FO4s of wire and gate delay between clock latches you can get more done and have to accept as many compromises in dividing your logic up, say 24 FO4s instead of the standard 16. Less timing overhead lost to the latches and clock jitter. And less pain and energy lost around distributing the clock signal in the first place. You'll never be able to clock as high as more highly pipelined designs but if you beat them through parallelism while using less power that's the design point you need in a mobile processor. You're losing some performance/transistor efficiency in your cores but those are a minority of your wafer size.