5 ms·

Why is the naive-bayes benchmark (first graph) such an extreme outlier? M1 is ~10 times slower on this benchmark whereas it is faster than the competition on a

Why is the naive-bayes benchmark (first graph) such an extreme outlier? M1 is ~10 times slower on this benchmark whereas it is faster than the competition on almost any other benchmarks.

gzer0 6y ago
The decoupling of the class conditional feature distributions of the naive-bayes benchmark means that each distribution can be independently estimated as a one-dimensional distribution. This helps alleviate problems stemming from the curse of dimensionality, such as the need for data sets that scale exponentially with the number of features. This is precisely an area where x86 architecture and CISC ISA will out rank the RISC-V ISA of M1's. But perhaps, I don't know what I am talking about. Someone with more knowledge, please chime in. [1] https://web.archive.org/web/20140311005243/http://machinelearning.wustl.edu/mlpapers/paper_files/icml2005_Niculescu-MizilC05.pdf https://web.archive.org/web/20140311005243/http://machinelea... [2] https://www.researchgate.net/publication/228845263_An_Empirical_Study_of_the_Naive_Bayes_Classifier https://www.researchgate.net/publication/228845263_An_Empiri...
- gpderetta 6y ago
  M1 is not RISC-V and I don't think CISC vs RISC is of any significance here. If naive bayes is really embarassingly parallel, SIMD+lots of cores help here of course. It is also probably highly optimized code that doesn't rely so significantly on OoO capabilities and can take advantage of the higher clock rate. Even Itanium was very good at numerical code.
  - gzer0 6y ago
    What is the M1 then? https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020... confused.
    - gpderetta 6y ago
      ARM. Which is a RISC architecture, but RISC-V is a specific RISC architecture distinct from ARM.
    - astrange 6y ago
      This article is very inaccurate about modern tradeoffs in ISAs and you should probably just forget you read it.
- deleted 6y ago
  [deleted]

Why is the naive-bayes benchmark (first graph) such an extreme outlier? M1 is ~10 times slower on this benchmark whereas it is faster than the competition on almost any other benchmarks.

gzer0 6y ago

The decoupling of the class conditional feature distributions of the naive-bayes benchmark means that each distribution can be independently estimated as a one-dimensional distribution. This helps alleviate problems stemming from the curse of dimensionality, such as the need for data sets that scale exponentially with the number of features. This is precisely an area where x86 architecture and CISC ISA will out rank the RISC-V ISA of M1's. But perhaps, I don't know what I am talking about. Someone with more knowledge, please chime in. [1] https://web.archive.org/web/20140311005243/http://machinelearning.wustl.edu/mlpapers/paper_files/icml2005_Niculescu-MizilC05.pdf https://web.archive.org/web/20140311005243/http://machinelea... [2] https://www.researchgate.net/publication/228845263_An_Empirical_Study_of_the_Naive_Bayes_Classifier https://www.researchgate.net/publication/228845263_An_Empiri...

gpderetta 6y ago
M1 is not RISC-V and I don't think CISC vs RISC is of any significance here. If naive bayes is really embarassingly parallel, SIMD+lots of cores help here of course. It is also probably highly optimized code that doesn't rely so significantly on OoO capabilities and can take advantage of the higher clock rate. Even Itanium was very good at numerical code.
- gzer0 6y ago
  What is the M1 then? https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020... confused.
  - gpderetta 6y ago
    ARM. Which is a RISC architecture, but RISC-V is a specific RISC architecture distinct from ARM.
  - astrange 6y ago
    This article is very inaccurate about modern tradeoffs in ISAs and you should probably just forget you read it.
deleted 6y ago
[deleted]