5 ms·
How does this square with their relatively low power consumption? (Honestly asking--I don't know about this stuff)
by nielsbot 6y ago
How does this square with their relatively low power consumption? (Honestly asking--I don't know about this stuff)
- userbinator 6y agoI suspect that's largely due to the smaller process size.
- ben-schaaf 6y agoTo add to this: TSMC states either 15% performance or 30% efficiency gains on 5nm (relative to 7nm). Applying the 30% efficiency gains to the similarly performing Zen 3 CPUs gets you to similar consumption as the M1 (in a load scenario, big little has idle advantages).
- GeekyBear 6y agoThe theory when the first Apple 5nm chip was announced is that Apple took the power efficiency gain. >The one explanation and theory I have is that Apple might have finally pulled back on their excessive peak power draw at the maximum performance states of the CPUs and GPUs, and thus peak performance wouldn’t have seen such a large jump this generation, but favour more sustainable thermal figures. Apple’s A12 and A13 chips were large performance upgrades both on the side of the CPU and GPU, however one criticism I had made of the company’s designs is that they both increased the power draw beyond what was usually sustainable in a mobile thermal envelope. This meant that while the designs had amazing peak performance figures, the chips were unable to sustain them for prolonged periods beyond 2-3 minutes. Keeping that in mind, the devices throttled to performance levels that were still ahead of the competition, leaving Apple in a leadership position in terms of efficiency. https://www.anandtech.com/show/16088/apple-announces-5nm-a14-soc-meagre-upgrades-or-less-power-hungry https://www.anandtech.com/show/16088/apple-announces-5nm-a14...
- syberslidder 6y agoSimilar to overall performance, power consumption has many factors. As others have pointed out, a new process is a big part of it. Additionally, they have very efficient and well designed small cores in their SoC and one benefit their full vertical integration is their OS has very good schedulers for maximizing time on small power-efficient cores without impacting performance in a noticeable way. At a core level, I assume they have very good clock and power gating, so even if the cores have these massive structures, they might be able to power down some or all of them. For instance, adding a 4th vector unit might seem expensive, but most workloads are not running vector instructions, so all 4 of those units can be powered off for the time slice that application is running. Apple also has very good physical design teams that produce custom macros for almost the entire chip, which individually are very minor but do add up significantly.