3 ms·
Saying it can process twice as many instructions per clock cycle is an incredibly incorrect statement. It's not as incredibly incorrect as you may think. An x
by alwillis 6y ago
Saying it can process twice as many instructions per clock cycle is an incredibly incorrect statement.
It's not as incredibly incorrect as you may think.
An x86 instruction can be as big as 15 bytes and there's no easy way for the decoder to know where one instruction ends and the next one begins.
All ARM instructions are one size, making instruction decoding more efficient and makes out of order processing faster as well.
More details at https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2 https://debugger.medium.com/why-is-apples-m1-chip-so-fast-32...
- jeffbee 6y agoYou keep posting this but it doesn't become more true just by posting it over and over again.
- reitzensteinm 6y agoParent's comment was about micro-op caches. Modern x86 processors in a relatively tight loop do not decode the instructions each iteration. I suspect you haven't internalized this, because reiterating the complexity of decoding instructions just isn't a valid response. The entire point is avoiding that cost.