2 ms·
The article is phrased confusingly, at one point saying there are 4 pipelines, and then saying it can do 4 FADDs and 4 FMULs(for a total of 8) per cycle. So a
by TinkersW 6y ago
The article is phrased confusingly, at one point saying there are 4 pipelines, and then saying it can do 4 FADDs and 4 FMULs(for a total of 8) per cycle.
So are there 4 or 8?? I believe what they meant to say was 4 FADDs OR 4 FMULs.
Then they say it has quadruple the throughput of Intel and older AMD chips, but that doesn't follow unless this does 8 floating point operations per cycle not 4.
The image of the pipeline only shows 4 so I think this is 4x128 wide, which is good but not going to compete with Zen3 with its wider registers. It is also not quadruple the throughput of Intel or AMD for SIMD..
- rayiner 6y agoEach is a multiply-accumulate instruction: https://developer.arm.com/documentation/dui0473/latest/neon-programming/fused-multiply-add-extension-for-neon https://developer.arm.com/documentation/dui0473/latest/neon-...
- TinkersW 6y agoThey probably are FMA ports, but they didn't say that anywhere in the article, and it still doesn't explain the "quadruple the throughput", as both of Intels ports are FMA and 2/4 of AMDs are FMA.
- deleted 6y ago[deleted]