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Anandtech's deep dive into Apple's Firestorm big cores is definitely worth reading if you are interested in how the chips that use their ARM implementation are

Anandtech's deep dive into Apple's Firestorm big cores is definitely worth reading if you are interested in how the chips that use their ARM implementation are different. >On the floating point and vector execution side of things, the new Firestorm cores are actually more impressive as they a 33% increase in capabilities, enabled by Apple’s addition of a fourth execution pipeline. The FP rename registers here seem to land at 384 entries, which is again comparatively massive. The four 128-bit NEON pipelines thus on paper match the current throughput capabilities of desktop cores from AMD and Intel, albeit with smaller vectors. Floating-point operations throughput here is 1:1 with the pipeline count, meaning Firestorm can do 4 FADDs and 4 FMULs per cycle with respectively 3 and 4 cycles latency. That’s quadruple the per-cycle throughput of Intel CPUs and previous AMD CPUs, and still double that of the recent Zen3, of course, still running at lower frequency. This might be one reason why Apples does so well in browser benchmarks (JavaScript numbers are floating-point doubles). Vector abilities of the 4 pipelines seem to be identical, with the only instructions that see lower throughput being FP divisions, reciprocals and square-root operations that only have an throughput of 1, on one of the four pipes. https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...

easde 6y ago
I like Apple's approach of having more narrow vector units rather than a few extremely wide ones. Narrower vector units are generally easier to program and easier to support on small cores (like the efficiency cores). It's a good tradeoff for cores used outside of niche applications that do a ton of numerical calculations. Compare this to a design like AVX/AVX2 that has wider 256-bit vectors, but almost always forces the programmer to treat them as two 128-bit vectors glued together. All because Intel realized they had to power down half of each vector ALU to save power at idle. Of course, the future is hopefully more flexible vector ISAs like SVE. AVX-512 is not too bad either today, but Intel seems almost pathologically opposed to making forward-looking decisions (what about when they want to double the vector width again??).
TinkersW 6y ago
The article is phrased confusingly, at one point saying there are 4 pipelines, and then saying it can do 4 FADDs and 4 FMULs(for a total of 8) per cycle. So are there 4 or 8?? I believe what they meant to say was 4 FADDs OR 4 FMULs. Then they say it has quadruple the throughput of Intel and older AMD chips, but that doesn't follow unless this does 8 floating point operations per cycle not 4. The image of the pipeline only shows 4 so I think this is 4x128 wide, which is good but not going to compete with Zen3 with its wider registers. It is also not quadruple the throughput of Intel or AMD for SIMD..
- rayiner 6y ago
  Each is a multiply-accumulate instruction: https://developer.arm.com/documentation/dui0473/latest/neon-programming/fused-multiply-add-extension-for-neon https://developer.arm.com/documentation/dui0473/latest/neon-...
  - TinkersW 6y ago
    They probably are FMA ports, but they didn't say that anywhere in the article, and it still doesn't explain the "quadruple the throughput", as both of Intels ports are FMA and 2/4 of AMDs are FMA.
- deleted 6y ago
  [deleted]

easde 6y ago

I like Apple's approach of having more narrow vector units rather than a few extremely wide ones. Narrower vector units are generally easier to program and easier to support on small cores (like the efficiency cores). It's a good tradeoff for cores used outside of niche applications that do a ton of numerical calculations. Compare this to a design like AVX/AVX2 that has wider 256-bit vectors, but almost always forces the programmer to treat them as two 128-bit vectors glued together. All because Intel realized they had to power down half of each vector ALU to save power at idle. Of course, the future is hopefully more flexible vector ISAs like SVE. AVX-512 is not too bad either today, but Intel seems almost pathologically opposed to making forward-looking decisions (what about when they want to double the vector width again??).

TinkersW 6y ago

The article is phrased confusingly, at one point saying there are 4 pipelines, and then saying it can do 4 FADDs and 4 FMULs(for a total of 8) per cycle. So are there 4 or 8?? I believe what they meant to say was 4 FADDs OR 4 FMULs. Then they say it has quadruple the throughput of Intel and older AMD chips, but that doesn't follow unless this does 8 floating point operations per cycle not 4. The image of the pipeline only shows 4 so I think this is 4x128 wide, which is good but not going to compete with Zen3 with its wider registers. It is also not quadruple the throughput of Intel or AMD for SIMD..

rayiner 6y ago
Each is a multiply-accumulate instruction: https://developer.arm.com/documentation/dui0473/latest/neon-programming/fused-multiply-add-extension-for-neon https://developer.arm.com/documentation/dui0473/latest/neon-...
- TinkersW 6y ago
  They probably are FMA ports, but they didn't say that anywhere in the article, and it still doesn't explain the "quadruple the throughput", as both of Intels ports are FMA and 2/4 of AMDs are FMA.
deleted 6y ago
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