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Older AMD CPUs, such as the K5 were RISC CPUs with an x86 decoding frontend: https://en.wikipedia.org/wiki/AMD_K5 https://en.wikipedia.org/wiki/AMD_K5
by danieldk 6y ago
Older AMD CPUs, such as the K5 were RISC CPUs with an x86 decoding frontend:
https://en.wikipedia.org/wiki/AMD_K5 https://en.wikipedia.org/wiki/AMD_K5
- lxgr 6y agoIsn't that arguably true for all modern x86 CPUs, including Intel's?
- mhh__ 6y agoThat is true, although it's worth saying that (if I'm not mistaken) outside of patents we don't really know what the micro-ops do i.e. RISC possibly isn't the best descriptor. The microarchitectural classification of a modern CPU is slightly murky, i.e. a modern x86 has a pipeline a la the first one to do so, but the way the CPU actually uses it is completely different (i.e. OoO, speculative etc.)