There is no need for advanced nodes for micro-controllers. Typically even advanced µC use 40nm, planar, where the TSMC leading node is 5nm FinFET. ST also does

There is no need for advanced nodes for micro-controllers. Typically even advanced µC use 40nm, planar, where the TSMC leading node is 5nm FinFET. ST also does FD-SOI 22nm if I remember well, but that's the densest node they have and nowhere near the current state of the art at TSMC. The thing is, micro-controllers do not need advanced nodes. They don't have a lot of logic (it's all relative, but compared to a PC CPU or smartphone SoC), so would be "pad limited" on advanced nodes: the area of a chip depends on the logic (and memory), but also on the I/O pins or pads, which take area. So if you used a too advanced node for a chip with (relatively) little logic and still enough I/O pads, some die area would be wasted as the minimum area would come from the pads. It's a situation you want to avoid, as there's no point paying for a more costly finer nodes (with more leakage) to waste it by not using the silicon area. Another factor is that micro-controllers also embed Flash on their die, to have a very integrated solution with logic, RAM and Flash storage on a single die. This puts a limit on the node density. Flash is OK down to 40nm. Then from then one must move to more advanced, and still young and costly, alternatives (MRAM). So if your business is driven by micro-controllers, there's no real point in pushing toward node density ("low" nodes). ST does process optimization as everyone, but at "medium" nodes best suited for µC. There's no business drive for them to chase TSMC. It's similar for other Eurpeans silicon makers: they tend to be on specific segments where going for "low" nodes like 5nm simply doesn't make sense. The relatively advanced fabs in Europe are from Intel and Global Foundries (both US). And GloFo stopped the race to advanced node at 14nm, as it was too expensive.